1. Field of the Invention
The present invention broadly relates to a method of analyzing faults and failures in the design of electronic apparatus and devices.
More specifically, the invention relates to a method wherein a DFMEA form or document is used for analyzing faults and failures in the design of electronic apparatus and devices, the DFMEA form including a data-entry mask through which information concerning the analysis are recorded and in which at least a portion of the document is displayed to a user in an electronic display format.
2. Description of the Related Art
As is well known in this technical field, one of the best appreciated and widely used techniques for preventing faults and/or errors in the design of apparatus and/or devices for automotive applications is a method commonly referred to by the acronym FMEA (Failure Mode Effect Analysis).
This method or technique was developed in the States for the automotive industry, but soon spread to the suppliers of the US automotive manufacturers.
In the FMEA technique, under the guidance of a predetermined form to be filled, the user is directed to identify possible weakness areas in a product or a process, and this especially at the initial development stage.
There are two main divisions in the FMEA technique: a first division covers industrial processes and is known as PFMEA (Process FMEA); a second division is specific to the design of new parts and/or devices and known as DFMEA (Design FMEA).
The analysis is conducted by means of a form divided into two sections, as specified here below.
A right-side section is devoted to illustrate a potential problem by the following entries:
Item/Function: identifies the part affected by the problem;
Potential Failure Mode: indicates a failure mode;
Effect of Failure: is the failure mode effect on the application and operation;
Root Cause: is the prime cause that originated the failure mode; and
Current Control: is an existing control for finding the failure mode.
Consort with these entries of a descriptive nature are three columns that are used for weighing the degree of risk that associates with each entry. The weight marks may be, for example:
S (Severity), to provide a measure of how severe the failure mode effect is;
O (Occurrence), to quantify the rate at which the failure mode is generated; and
D (Detectivity), to detect the location within the control chain where the failure mode can be found.
All these marks carry a value scale from 1 to 10, with 1 being the lowest and 10 the highest degree of risk.
On completion of a preliminary analysis, a Risk Product Number (RPN) is arrived at by multiplying the marks S, O, D together, this number indicating the degree of risk that associates with the potential failure mode detected.
When RPN exceeds a given threshold value, corrective actions must be taken to bring it down.
The second section of the form, which is reserved for the last-mentioned entry, comprises:
Recommended Action: the action proposed in order to bring RPN down;
Responsible and Completion Date: the responsible entity for the action and the action completion date; and
Action Taken: the action actually completed.
The three columns labeled S, O and D and to be re-calculated after completion of the corrective action specified, should be added to these columns.
The FMEA technique outlined above has gained widespread acceptance in the semiconductor industry. However, this is an industry devoted to the production of highly complex devices whose component parts to be analyzed may be millions.
The FMEA technique has been perfected under the concurrent urge of quality requirements enforced by a number of protocols, such as the QS9000 protocol.
Initially, the PFMEA technique grew in popularity, while the other DFMEA technique was only occasionally applied, but later the DFMEA technique would prove to be the more useful and profitable for the manufacturer. The few examples in existence only regard its use at meetings, or to fill demands arising from auditing operations or the like scrutinizing operations.
The reasons for this initial lack of interest in the DFMEA technique are summarized here below.
Any attempt to apply a DFMEA technique based upon the potential failure modes of individual elements included into a complex device is unthinkable and Utopian. Even a potential demand from clients and quality control groups missed to reflect the practical difficulties faced by the designer.
Even if one or more component parts were analyzed, the reference grid for reckoning the S, O, D marks would approach a process analysis in a fashion far too sweeping, thereby occasioning interpretation difficulties making the reckoning ineffective.
The types of information that describe the aforementioned fields (e.g., Action Taken, Potential Failure Mode, etc.) often require that detailed descriptions and attendant graphs, diagrams, etc., be submitted which are impossible to abridge in a text like the one provided for in the known form. The suggestion to give a numeral reference to technical reports makes their retrieval a difficult, laborious and inefficient task, so that people are discouraged from attempting to read and understand a DFMEA.
The environment where the DFMEA technique was originally developed is that of an international holding where similar devices, potentially sharing the same recurrent problems, are frequently developed by different designing departments residing in different, towns, territories, or nations.
To summarize, while being advantageous on several counts, the DFMEA technique has limitations that delay its application by the designers of electronic apparatus and devices. Of these limitations, the following are more heavily felt:
current rules that cannot be applied to highly complex devices;
reference grids for the S, O, D mark that do not match the designing criteria;
no provisions for the inclusion of technical information in a text; and
information that is difficult to have circulated through all the product development teams involved.